Artificial Intelligence in Logic Design by Svetlana N. Yanushkevich (auth.)

By Svetlana N. Yanushkevich (auth.)

There are 3 impressive issues of this booklet. First: for the 1st time, a collective perspective at the position of synthetic intelligence paradigm in common sense layout is brought. moment, the ebook unearths new horizons of good judgment layout instruments at the applied sciences of the close to destiny. eventually, the individuals of the ebook are twenty recognizable leaders within the box from the seven learn centres. The chapters of the e-book were conscientiously reviewed by way of both certified specialists. All individuals are skilled in useful digital layout and in educating engineering classes. therefore, the book's type is available to graduate scholars, functional engineers and researchers.

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G -- '. - ··. ··'.. id - . ~ , Transistor count: 3042 i> i >. I. -" . • .. =>. ~ Number of counter stages: 4 a r-t:: -i- i • r-~: ~ ".... ',.. t >• -, '. ". " Bias canceling stage (a) Transistor count: 3374 '. "'. >- Bias canceling stage (b) Figure 9. Multiplier configurations corresponding to the graphs of Figure 8: (a) the best solution generated by EGG system, (b) the CSD multiplier using Wallace tree architecture. in signal processing applications. The target function Y = K X is the same as that used in the previous section.

1999; Haddow and Tufte 2000; Tyrrell et al. 2001). Their main motivation is based on the hypothesis that the evolutionary algorithms would inevitably explore a much richer set of possibilities in the design space that are beyond the scope of conventional methods (Thompson et al. 1999). Reference (Miller et al. 1997), for example, presents a GA-based circuit synthesis technique that is capable of evolving 100% functional arithmetic circuits and is closely related to this work. The reported design method, however, is based on direct evolution with gate-level primitive components such as logic gates and flip-flops.

In this experiment, the EGG system synthesizes the multiplier structure without using the knowledge of the above techniques. Figure 10 shows the five types of nodes in this experiment. Each node represents a bit-level arithmetic component such as I-bit full adders and I-bit registers. The EGG system is designed to generate complete circuit graphs with feedback loops in the evolution process since the target circuit to be synthesized belongs to the class of sequential circuits. Thus, the variation of possible graph structures is larger than the previous example (which assumes CCTs: Complete Circuit Trees).

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