Algorithmically Specialized Parallel Computers by Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon

By Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon

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Similarly, connecting UBDOUT of the i t h cell to BDIN of the i + lst cell. Hence, data flows to the "right" during PUSH operations, and to the "left" during POP operations. 1. COMPARE/EXCHANGE Cell Block Diagram. As mentioned above, the contents of the two cells are compared during clock phase 2 (PHI2). If a match occurs, the EXCHIN signal is propagated. If a mismatch occurs, EXCHOUT will be the inverted value of the rightmost bit (signaling that an exchange is needed if the rightmost bit is "0").

Performance Estimates This section of our report discusses the performance of the RESST chip. We examined the timing of each of the clock phases using simple SPICE models of the salient portions of our circuit. ) We also briefly considered the power consumption of the design. The results of these performance estimates will be summarized here, with further details available in [Car82]. 1. Timing Estimates During phase 1. data is PUSHed or POPped from the RESST chip. This involves getting data on and off the chip, getting phase 1 clocked signals distributed throughout the chip, shifting data from cell to cell, and allowing the carry-chain-like EXCHIN/EXCHOUT signal to ripple from the least to the most significant bit (worst case).

UCB/ERL M82/5, University of California, Berkeley. 1982. [U1180] Ullman. J.. "Principles of Database Systems", Computer Science Press, 1980. A Pipelined Architecture for Search Tree Maintenance Michael J. Carey Clark D. Thompson Computer Science Division Department of Electrical Engineering and Computer Science University of California Berkeley, CA 94720 ABSTRACT A scheme for maintaining a balanced search tree on 0{lgN) parallel processors is described. 0(lgN) search, insert, and delete operations are allowed to run concurrently, with each operation executing in 0(lgN) timesteps.

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