By Marshall C. Yovits
Comprises long assessment articles on desktop aided common sense synthesis for VLSI chips, sensor-driven clever robotics, complex ideas in dealing with allotted facts, details circulation and keep watch over among people and desktops and automatic vote casting.
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Extra resources for Advances in Computers, Vol. 32
Suppose a network in Fig. 1l(b) is designed by some means to realize function f(xl, x2, x3) = (01*10*11). The output function realized at each gate vi in Fig. 11. Permissible functions of a network. i 0 1 * 1 0 * 1 1 36 SABURO MUROGA Fig. 1l(a). The columns in Fig. 11(a) are shown horizontally as vectors in Fig. 1l(b). For example, the output function of gate v 5 , f ( v 5 ) ,is shown by vector (00001000)placed just outside gate v 5 in Fig. ll(b). , *'s), whereas the output function f(u4) (denoted by f without a dot on top of it) of gate u4, for example, in the actually realized network in Fig.
Suppose any outputs of the network do not 37 COMPUTER-AIDED LOGIC SYNTHESIS FOR VLSl CHIPS TABLE I1 TRUTHTABLE X1 0 0 0 0 ... ... xn-1 xn ... 0 0 0 I ... 1 1 ... f(ui) 91 ~2 g3 1 1 ... 1 1 1 1 1 0 0 0 1 0 1 0 0 0 0 ... ... 0 gh 1 c(ui) 1 * ... ... 0 0 ... * ... ... change even if this function f(ui) in Table I1 is replaced by g1 = (1100. ), g2 = (1000.. ), .... or gh shown in Table 11. In other words, g l , . gh are permissible functions. ) Then, permissible functions g1through gh can be expressed by a single vector C(ui)= (1* *O ..
1 simplifies the initial network shown in Fig. lO(a),as an example. By a transformation (more precisely speaking, transformation called connectable condition, which is explained later), we have the new network shown in Fig. 10(b), by connecting the output of gate 0 6 to the gate ug (shown in bold lines). By the pruning procedure, the connection from gate us to gate u4 (shown in a dotted line) is deleted, deriving the new network shown in Fig. 1O(c),and then the connection from gate vg to gate u6 is deleted, deriving the new network shown in Fig.